On July 30, 2026, Openchip introduced BER10, a 64-bit processor developed in Spain using the open RISC-V architecture. The Barcelona-based semiconductor company, founded in 2021, develops chips for high-performance computing (HPC) and artificial intelligence. After about two and a half years of engineering, BER10 is ready for companies and research centers to test and validate in HPC projects. The design was taped out in 2025, and functional samples were obtained in 2026. Openchip describes it as Europe’s first RISC-V chip for supercomputing.
BER10 is working silicon, not a design that exists only in simulation. It can run a complete Linux operating system and uses Gate-All-Around technology at under 2 nanometers. EET China’s technical coverage also describes the processor as using a sub-2-nanometer process and identifies it as a server-oriented RISC-V chip. Functional samples mark a development key stage and give companies a platform for validation. That is distinct from mass production or demonstrated commercial performance.
Advanced Architecture
The processor has four high-performance cores that support out-of-order execution and simultaneous operations, allowing it to handle complex tasks efficiently. The architecture lets the chip keep processing while slower operations are pending, a useful capability for demanding server and data-center workloads.
One of BER10’s standout components is its vector unit, designed to accelerate parallel calculations. Openchip has tailored it for AI and scientific computing, including image processing, where rapid handling of large datasets is impressive. The chip also integrates fast multi-channel memory, along with high-speed PCIe and AXI connections intended to support compatibility with hardware ecosystems used in modern data centers.
Openchip has yet to release clock speeds or pricing, and has not disclosed power consumption or direct performance comparisons. The company says BER10 is ready for real-world validation and software development. Those steps will show how the processor performs on specific workloads. A functional sample alone does not establish competitiveness with established x86 or Arm server processors.
Open Standards, European Control
RISC-V, the open instruction-set architecture at BER10’s basic, lets companies design processors without paying licensing fees for the architecture. That flexibility gives European firms and institutions room to develop chips for their needs and may reduce reliance on architectures controlled by foreign suppliers. The instruction set itself, but, does not determine where a chip is fabricated or establish commercial readiness or supply-chain independence.
RISC-V is open, but manufacturers can keep some design elements proprietary. Openchip combines the open standard with protected innovations, aiming to balance transparency with edge.
The company argues that this model strengthens Europe’s technological sovereignty, particularly in government and banking, as well as healthcare and critical infrastructure, where control over hardware is increasingly impressive. BER10 is part of a broader effort to develop European processors for data-center and HPC applications.
Openchip is entering a field that includes SiFive’s BigSky and Tenstorrent’s Atlantis, as well as Epic Semi’s Contrail AIX, NextSilicon’s Arbel, and SpacemiT’s V100. NeoTeo’s comparison stresses that these projects are at different development stages, not results from a shared performance test. Their names alone, so, do not establish a performance ranking.
Ready for Deployment
BER10 is a physical, working chip that partner companies and computing centers can use to develop software, test workloads, and assess compatibility with the RISC-V environment ahead of later products. Openchip CEO Cesc Guim has described the key stage as evidence that Europe can produce advanced silicon based on open standards. The chip is intended as a platform for developing new RISC-V accelerators for AI and supercomputing, as well as data-center applications.
Openchip’s HPC and AI work is also part of a wider collaboration with French processor company Kalray. On October 14, 2026, the companies extended their partnership for 12 months in an agreement reported to be worth approximately €5 million. Kalray’s expertise will continue to support development of Openchip’s next-generation HPC and AI chips, and Openchip became a Kalray shareholder during the summer of 2026. Kalray reported consolidated 2025 revenue of €16.45 million and a workforce of 128 employees as of June 30, 2025. Those figures provide context for the partnership, not BER10 sales or production metrics.
As data infrastructure expands, debates over land use and resource consumption are growing too. Cases such as landowners rejecting lucrative offers for data-center construction reflect the sector’s increasing impact on local communities.
Major Public Investment
On June 29, 2026, Spain’s Council of Ministers approved an investment of more than €115 million in Openchip through the Sociedad Española para la Cambio Tecnológica (SETT). The funding is intended to accelerate the design and commercialization of high-performance, energy-efficient chips for AI and supercomputing.
Openchip has received around €261 million in total public support, including €111 million from the PERTE Chip initiative and €35 million from the Generalitat of Catalonia. Founded in 2021 by the Barcelona Supercomputing Center and GTD Software Engineering, the company now employs about 300 people. Public investment is tied to job creation and development of a European semiconductor industry.
Openchip’s announcement says BER10 has moved beyond the design phase and can now run real software. The company has not disclosed when large-scale commercial production will begin or which manufacturers will handle future processor fabrication.
As Europe seeks greater independence in advanced technology, BER10 is a step toward building a homegrown environment for high-performance computing and artificial intelligence. The next test is whether validation and software development can turn the working silicon into a commercially deployable platform.
